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The Draftsbook Blog

Articles, deep dives, and notes from the engineering community.

Part 7: Cloud Computing Security, Data Protection & CASB Architecture
Nov 5, 20263 min read

Part 7: Cloud Computing Security, Data Protection & CASB Architecture

A masterclass in cloud security: explore Zero Trust architecture, IAM least privilege, KMS envelope encryption, and Cloud Access Security Brokers (CASB).

By Md. Harun-Or-Roshid

Part 7: Query Execution Engines: Volcano Iterators & Cost-Based Optimization
Nov 5, 20263 min read

Part 7: Query Execution Engines: Volcano Iterators & Cost-Based Optimization

Explore database query execution engines: Volcano iterator models, physical join algorithms (Hash vs Sort-Merge), and cost-based plan optimization.

By Md. Harun-Or-Roshid

Part 9: Clipping Algorithms: Cohen-Sutherland Line & Sutherland-Hodgman Polygon
Nov 5, 20263 min read

Part 9: Clipping Algorithms: Cohen-Sutherland Line & Sutherland-Hodgman Polygon

A deep analysis of 2D geometric clipping algorithms, detailing Cohen-Sutherland 4-bit region outcodes and Sutherland-Hodgman sequential polygon clipping.

By Md. Harun-Or-Roshid

Part 9: Assembly Arrays, String Primitives & Hardware Streaming (REP MOVSB)
Nov 5, 20263 min read

Part 9: Assembly Arrays, String Primitives & Hardware Streaming (REP MOVSB)

Master memory buffers and strings in x86-64 assembly: arrays, strides, and hardware block primitives including MOVSB, LODSB, STOSB, SCASB, and REP.

By Md. Harun-Or-Roshid

Part 8: Instruction Set Architecture: CISC vs RISC & The Open RISC-V Standard
Nov 5, 20263 min read

Part 8: Instruction Set Architecture: CISC vs RISC & The Open RISC-V Standard

A masterclass in computer instruction set architectures, comparing x86 CISC with ARM, evaluating the Iron Law of CPU performance, and exploring modular open RISC-V.

By Md. Harun-Or-Roshid

Part 7: Systems Development Life Cycle (SDLC): Agile, DevOps & Design
Nov 5, 20263 min read

Part 7: Systems Development Life Cycle (SDLC): Agile, DevOps & Design

Master the Systems Development Life Cycle (SDLC): TELOS feasibility, Waterfall vs Agile Scrum, CI/CD automated deployment, and enterprise DevOps.

By Md. Harun-Or-Roshid

Part 6: Routing Packets Across the Internet: Autonomous Systems, BGP & OSPF
Nov 5, 20263 min read

Part 6: Routing Packets Across the Internet: Autonomous Systems, BGP & OSPF

Demystify global internet routing, exploring Autonomous Systems, Border Gateway Protocol (BGP-4), interior routing with OSPF, and CIDR subnetting.

By Md. Harun-Or-Roshid

Part 7: Pulse Modulation & Companding: PAM, PWM, PPM, PCM & Quantization
Nov 5, 20262 min read

Part 7: Pulse Modulation & Companding: PAM, PWM, PPM, PCM & Quantization

Explore analog-to-digital signal conversion: comparing PAM, PWM, PPM, Pulse Code Modulation (PCM) sampling, quantization error, and µ-law/A-law companding.

By Md. Harun-Or-Roshid

Part 8: Conditional Branching, Jump Instructions & Fast Loops in Assembly
Nov 5, 20263 min read

Part 8: Conditional Branching, Jump Instructions & Fast Loops in Assembly

Learn how conditional jumps work in x86-64 assembly using CMP, TEST, JE, JNE, JG, JL, JA, JB, and write high-performance loops with branch prediction.

By Md. Harun-Or-Roshid

Part 8: 2D Viewing Pipeline: Window-to-Viewport Transformation Coordinates
Nov 5, 20263 min read

Part 8: 2D Viewing Pipeline: Window-to-Viewport Transformation Coordinates

A study of the 2D viewing transformation pipeline, detailing coordinate normalization, world window to viewport scaling derivation, and aspect ratio preservation.

By Md. Harun-Or-Roshid

Part 6: Cloud Management, Storage, Virtualization & Resource Provisioning
Nov 5, 20263 min read

Part 6: Cloud Management, Storage, Virtualization & Resource Provisioning

A deep dive into cloud virtualization and storage: analyze Type-1 hypervisors, MicroVMs, and block (EBS), object (S3), and file (EFS) architectures.

By Md. Harun-Or-Roshid

Part 5: Packet Switching vs Circuit Switching: Bandwidth, Latency & Queueing Delays
Nov 5, 20263 min read

Part 5: Packet Switching vs Circuit Switching: Bandwidth, Latency & Queueing Delays

Compare packet switching and circuit switching architectures, examining statistical multiplexing, router buffer queues, packet loss, and jitter.

By Md. Harun-Or-Roshid