Packet Switching vs Circuit Switching Latency

Lesson Overview & Learning Objectives

The fundamental design choice that made the global internet possible was the departure from traditional telephone networks: replacing Circuit Switching with Packet Switching. While telephone networks physically lock dedicated transmission capacity for the duration of a call, the internet breaks data into independent chunks called packets, dynamically sharing transmission lines across millions of concurrent users. In this article, we contrast these two foundational architectures, explore the power of statistical multiplexing, analyze the four components of network delay, and inspect queueing bufferbloat.

1. Architectural Comparison: Dedicated Pipes vs. Shared Chunks

Dimension	Circuit Switching (Legacy Telecom)	Packet Switching (The Modern Internet)
Channel Allocation	Dedicated physical circuit reserved for session duration	Shared transmission medium (Statistical Multiplexing)
Bandwidth Utilization	Inefficient: silence and idle gaps waste reserved capacity	Highly efficient: line is utilized whenever any user sends data
Call Setup Latency	Mandatory end-to-end circuit setup delay before data transfer	Immediate packet dispatch without path reservation
Failure Resilience	Vulnerable: if any switch along circuit fails, call drops	Self-healing: subsequent packets dynamically route around failed nodes
Congestion Behavior	Call blocking (busy tone if circuits are full)	Increased queueing delay, jitter, and potential packet drop

2. The Power of Statistical Multiplexing

Imagine a 1 Gbps fiber link. Suppose typical web users generate traffic in bursty patterns—actively transmitting data only 10% of the time, remaining idle 90% of the time.

Under Circuit Switching

If each user requires 100 Mbps, the circuit-switched network can support exactly 10 users (10 × 100 Mbps = 1 Gbps), regardless of whether those users are actively talking or silent.

Under Packet Switching

Because the probability of all users transmitting simultaneously is negligible, the packet-switched network can comfortably support 50 to 100 users with indistinguishable performance! This multiplicative efficiency enabled the economic scaling of the global web.

3. The Four Pillars of Total Network Latency

Whenever an engineer benchmarks API latency, total delay is the exact sum of four physical and computational delays:

1. Nodal Processing Delay (d_proc)

The time router silicon takes to inspect the packet header, verify the IP checksum, evaluate firewall ACLs, and query the Forwarding Information Base (FIB). Typically under microseconds in modern hardware.

2. Queueing Delay (d_queue)

The time a packet sits in the router's memory buffer waiting for preceding packets to be transmitted onto the physical link. If inbound traffic exceeds outbound line capacity, queueing delay spikes and excess packets are dropped (Tail Drop).

3. Transmission Delay (d_trans = Length / Rate)

The time required to push all packet bits onto the physical medium. For a 1500-byte packet on a 1 Gbps link, transmission delay is 12 microseconds; on an old 10 Mbps link, it is 1.2 milliseconds.

4. Propagation Delay (d_prop = Distance / Speed)

The time a photon takes to travel the physical distance through silica fiber optics (approximately 5 microseconds per kilometer). Between New York and London (~5,500 km), pure propagation delay is roughly 28 milliseconds.