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The Draftsbook Blog

Articles, deep dives, and notes from the engineering community.

Part 5: 8085 Assembly Language Programming: Practical Algorithms, Arithmetic Routines, and Memory Manipulation
Mar 1, 20265 min read

Part 5: 8085 Assembly Language Programming: Practical Algorithms, Arithmetic Routines, and Memory Manipulation

A hands-on engineering guide to 8085 assembly programming: 8-bit and 16-bit multi-byte addition/subtraction with carry, array searching, bubble sort algorithms, and calibrated hardware delay loop calculations.

By Md. Harun-Or-Roshid

Part 4: Intel 8085 Instruction Set and Addressing Modes: Data Formats, Opcodes, and Machine Cycles
Mar 1, 20264 min read

Part 4: Intel 8085 Instruction Set and Addressing Modes: Data Formats, Opcodes, and Machine Cycles

A masterclass on the 8085 instruction set architecture: 1-byte, 2-byte, and 3-byte instruction formats, the 5 addressing modes, functional instruction groups, and T-state machine cycle timing.

By Md. Harun-Or-Roshid

Part 3: Intel 8085 Microprocessor Architecture: Internal Hardware, Registers, and Bus Demultiplexing
Mar 1, 20265 min read

Part 3: Intel 8085 Microprocessor Architecture: Internal Hardware, Registers, and Bus Demultiplexing

Comprehensive architectural analysis of the Intel 8085 CPU: functional block diagram, ALU, the 5 status flags, general and special purpose registers, timing & control unit, and address bus demultiplexing using a 74LS373 latch.

By Md. Harun-Or-Roshid

Part 2: Taxonomy of Microprocessors: CISC, RISC, EPIC, Vector, and Multicore Architectures
Mar 1, 20264 min read

Part 2: Taxonomy of Microprocessors: CISC, RISC, EPIC, Vector, and Multicore Architectures

A deep dive into processor classification architectures. Contrast CISC versus RISC design philosophies, explore EPIC, Vector, SIMD Array processors, and superscalar instruction-level parallelism.

By Md. Harun-Or-Roshid

Part 1: Microprocessor Evolution, Architectural Generations, and Operating Fundamentals
Mar 1, 20265 min read

Part 1: Microprocessor Evolution, Architectural Generations, and Operating Fundamentals

A foundational exploration of microprocessor architecture, tracing five decades of silicon evolution from the 4-bit Intel 4004 to modern multicore SoCs, alongside key performance metrics and the fundamental machine cycle.

By Md. Harun-Or-Roshid

Part 1: The HTML5 Semantic Document Tree: Semantic Tags, ARIA & SEO Architecture
Mar 1, 20269 min read

Part 1: The HTML5 Semantic Document Tree: Semantic Tags, ARIA & SEO Architecture

Master the HTML5 semantic document tree, modern layout tags, ARIA landmark roles, and search engine optimization principles for accessible web engineering.

By Md. Harun-Or-Roshid