Part 2: Taxonomy of Microprocessors: CISC, RISC, EPIC, Vector, and Multicore Architectures
The Architectural Divide
The design of a microprocessor's instruction set architecture (ISA) dictates every aspect of its physical silicon implementation—from register count and decoder complexity to thermal dissipation and compiler requirements. In Part 2 of our series, we contrast the two defining computing philosophies: Complex Instruction Set Computers (CISC) and Reduced Instruction Set Computers (RISC). We further explore specialized execution paradigms, including Explicitly Parallel Instruction Computing (EPIC), Vector and SIMD Array processors, and Digital Signal Processors (DSPs).
1. The CISC vs. RISC Paradigm
The historical battle between CISC and RISC represents differing answers to a core hardware-software trade-off: Should the silicon hardware carry the burden of executing complex, multi-step operations (CISC), or should the hardware remain streamlined and minimal, delegating optimization to an intelligent optimizing software compiler (RISC)?
CISC Philosophy
Hardware-Centric
CISC emerged in the 1970s when memory (magnetic core and early semiconductor RAM) was extraordinarily scarce and expensive. To minimize memory consumption, designers created rich instruction sets containing hundreds of specialized instructions. A single CISC instruction (such as MULT 2050H, 2060H) could fetch operands from memory, perform multiplication, and store the result back to memory across multiple clock cycles.
- Variable-length instruction encoding (1 to 15 bytes in x86).
- Extensive, complex addressing modes.
- Extensive use of microcode ROM decoders.
- Memory-to-memory and register-to-memory operations.
Canonical Examples: Intel 8085, 8086, 80386, x86-64, Motorola 68000.
RISC Philosophy
Compiler-CentricPioneered by John Cocke (IBM), David Patterson (UC Berkeley), and John Hennessy (Stanford) in the 1980s, RISC recognized that 80% of computer programs rely on a simple 20% subset of basic instructions. By discarding complex microcode instructions and hardwiring only simple, single-cycle primitives, CPU designers gained silicon real estate for dozens of general-purpose registers and deep execution pipelines.
- Strict fixed-length instructions (typically 32 bits).
- Pure Load/Store architecture (arithmetic operates exclusively on registers).
- Hardwired control logic without microcode overhead.
- Single-cycle throughput via balanced pipelining ($CPI \approx 1.0$).
Canonical Examples: ARM Cortex, MIPS, RISC-V, SPARC, PowerPC.
2. Exhaustive Comparison Matrix: CISC vs. RISC
| Evaluation Parameter | CISC (Complex Instruction Set) | RISC (Reduced Instruction Set) |
|---|---|---|
| Instruction Length | Variable (e.g., 1 to 15 bytes) | Fixed (typically 32 bits / 4 bytes) |
| Execution Time | Multi-clock cycle (varies widely per opcode) | Single clock cycle per pipeline stage |
| Control Unit Implementation | Microprogrammed control unit (Microcode ROM) | Hardwired combinatorial logic |
| Memory Access | Direct memory operands inside ALU instructions | Load/Store only (ALU operates purely on registers) |
| General-Purpose Registers | Fewer registers (8 to 16 typical) | Large register array (32 to 128+ registers) |
| Pipelining Efficiency | Difficult to pipeline due to irregular instruction lengths | Highly efficient and naturally pipelined |
| Code Density | High (compact binaries require less ROM space) | Lower (programs require more total instruction words) |
| Compiler Complexity | Simpler compiler; hardware interprets complex intent | Sophisticated compiler required for instruction scheduling |
3. Specialized Microprocessor Architectures
1. EPIC (Explicitly Parallel Instruction Computing)
Developed jointly by HP and Intel for the 64-bit Itanium (IA-64) processor family, EPIC shifts the burden of instruction-level parallel scheduling from hardware runtime decoders entirely to the software compiler. Instructions are packed into 128-bit bundles containing three 41-bit instructions and a 5-bit template field that explicitly designates which instructions can execute concurrently without data dependencies.
2. Vector & SIMD Array Processors
Traditional scalar microprocessors process one single data pair at a time (SISD: Single Instruction, Single Data). In contrast, Vector Processors and SIMD (Single Instruction, Multiple Data) engines execute one single instruction over massive one-dimensional arrays (vectors) of numeric elements simultaneously.
Modern iterations of this architecture underpin GPU compute units, Intel AVX-512, and ARM Neon multimedia engines, accelerating scientific simulations, 3D graphics rendering, video encoding, and deep neural network matrix multiplications.
3. Digital Signal Processors (DSP)
DSPs are microprocessors specialized for processing real-time analog signals digitized into numerical continuous data streams (audio filtering, speech synthesis, radar, RF telecommunications). DSPs feature dedicated single-cycle Multiply-Accumulate (MAC) hardware units, modified Harvard memory architectures (allowing concurrent instruction fetch and dual data operand reads), and hardware circular buffer addressing.
4. Scalar vs. Superscalar Architectures
A scalar processor processes at most one instruction per clock cycle through its execution pipeline. In contrast, a superscalar processor incorporates multiple parallel execution units (multiple ALUs, floating-point units, branch predictors, load/store units) fed by a hardware instruction dispatcher capable of issuing two, four, or eight instructions concurrently during a single clock cycle ($CPI < 1.0$, or $IPC > 1.0$).
Summary & Next Step
Having surveyed general processor taxonomy, we now shift our focus to concrete hardware silicon. In Part 3, we dissect the internal functional blocks, register architecture, flag register logic, and bus demultiplexing of the classic Intel 8085 microprocessor.
Related reading
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Part 10: Multiprocessor Configurations, 8087 Numeric Coprocessor, and Memory/IO Interfacing
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