Part 10: Multiprocessor Configurations, 8087 Numeric Coprocessor, and Memory/IO Interfacing
Scaling Beyond a Single CPU
Single-core microprocessors face physical processing limits when managing high-speed scientific floating-point math, massive peripheral data streams, or concurrent control loops. To address these demands, Intel engineered the 8086 with native multiprocessor capabilities in Maximum Mode. In Part 10, we contrast closely coupled and loosely coupled multiprocessor architectures, detail the coprocessor handshaking protocol of the Intel 8087 Numeric Data Processor (NDP), examine hardware bus arbitration mechanisms, and compare memory-mapped versus isolated I/O interfacing.
1. Closely Coupled vs. Loosely Coupled Systems
Closely Coupled Configuration
Shared Memory & ClockProcessors share a common system bus, system clock generator, and physical memory address space. Typically configured as a Host CPU (8086) paired with a specialized hardware coprocessor (e.g. Intel 8087 math coprocessor or Intel 8089 I/O processor).
- Zero communication latency across internal buses.
- Tightly synchronized instruction decoding via the
ESC(Escape) instruction. - Handshaking mediated via hardware pins:
TEST#,BUSY,RQ#/GT#.
Loosely Coupled Configuration
Distributed SystemsEach processor operates as an independent autonomous computational node with its own local memory, clock generator, and local I/O peripherals. Nodes interact over a shared common system bus or high-speed serial/parallel communication channels.
- Independent operating systems and clock domains.
- Communication achieved via shared multiport RAM or message passing.
- High fault tolerance: failure of one node does not crash the entire cluster.
2. The Intel 8087 Numeric Data Processor (NDP)
The Intel 8087 is an 80-bit numeric coprocessor capable of executing 32-bit/64-bit/80-bit IEEE 754 floating-point arithmetic (multiplication, division, square roots, logarithms, trigonometric functions) up to 100 times faster than software emulation routines running on the 8086.
The Coprocessor Execution Handshake Protocol
- Parallel Instruction Monitoring: In Maximum Mode, the 8087 monitors the status pins ($S_0-S_2$, $QS_0-QS_1$) and bus lines in lockstep with the 8086.
- The Escape (
ESC) Opcode: When the 8086 fetches an instruction with an opcode betweenD8HandDFH(theESCprefix), both processors recognize it as a floating-point instruction. - Memory Operand Coordination: If the instruction requires a memory operand, the 8086 calculates the 20-bit physical address and initiates the memory read. The 8087 latches the incoming data operand directly off the bus into its internal 80-bit register stack ($ST(0) - ST(7)$).
- Concurrent Computation & BUSY Pin: The 8087 begins floating-point computation, immediately pulling its
BUSYoutput pin HIGH. The 8086 continues executing subsequent integer instructions concurrently. - Synchronization via
WAITandTEST#: If the 8086 encounters a subsequent instruction requiring the floating-point result, the compiler inserts aWAIT(FWAIT) instruction. The 8086 samples itsTEST#pin (connected to 8087'sBUSY) and idles in wait states until the 8087 completes computation and dropsBUSYLOW.
3. Hardware Bus Arbitration Schemes
When multiple bus masters (multiple CPUs, DMA controllers) share a single common system bus, hardware arbitration is required to prevent electrical contention:
- Daisy Chaining (Serial Arbitration): Masters assert a common Bus Request line. The bus controller passes a Bus Grant signal serially down a chain of processors. The first processor in the chain requesting the bus intercepts the grant; lower-priority downstream devices must wait. Simple wiring, but priority is fixed by physical board geometry.
- Polling Scheme: The bus controller sequences through binary addresses of processors over polling lines. When a processor sees its address on the polling bus, it asserts its response and seizes the bus. Allows programmable priority rotations.
- Independent Request Scheme: Each master possesses dedicated Bus Request and Bus Grant lines routed to a central hardware arbiter (e.g., Intel 8289 Bus Arbiter). Yields the fastest arbitration and supports sophisticated dynamic priority algorithms.
4. Memory-Mapped I/O vs. I/O-Mapped (Isolated) I/O
| Feature | Memory-Mapped I/O | I/O-Mapped (Isolated) I/O |
|---|---|---|
| Address Space | Shared: I/O devices occupy portions of the memory address space (reduces available RAM). | Isolated: Dedicated 64 KB I/O address space separate from 1 MB memory space. |
| Control Signals | Standard memory strobes: $\overline{\text{MEMR}}$, $\overline{\text{MEMW}}$ | Dedicated I/O strobes: $\overline{\text{IOR}}$, $\overline{\text{IOW}}$ (governed by $\text{M}/\overline{\text{IO}}$) |
| Instructions Available | All memory instructions (MOV, ADD, CMP, AND) can operate directly on peripheral ports. | Restricted strictly to dedicated transfer instructions: IN and OUT. |
| Address Bus Width | Full 16-bit or 20-bit address bus | 8-bit ($256$ ports) or 16-bit ($65,536$ ports) using DX register |
| Hardware Decoding | More complex decoding logic (decodes 16 to 20 bits) | Simpler decoding logic (often only decodes lower 8 bits) |
Summary & Next Step
In Part 11, we shift from general-purpose microprocessors to dedicated embedded silicon: the Intel 8051 Microcontroller Architecture, detailing its Harvard memory structure, Special Function Registers (SFRs), and internal I/O port circuits.
Related reading
Part 12: Programmable Peripheral Interface ICs: Architecture and Pin Configuration of 8255, 8259, 8254, 8251, and 8257
The ultimate hardware reference for microprocessor peripheral interface adapters: complete architecture, pin configurations, and control word programming for the 8255 PPI, 8259 PIC, 8254 PIT, 8251 USART, and 8257 DMA controller.
By Md. Harun-Or-Roshid
Part 11: Intel 8051 Microcontroller Architecture: Harvard Memory Map, SFRs, and I/O Port Circuits
A master-level architectural analysis of the Intel 8051 microcontroller: Microprocessor vs Microcontroller paradigm, Harvard memory organization, 128-byte internal RAM layout, SFR registers, and internal circuits of Ports 0–3.
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Part 9: Interrupt Structures and Vector Pointer Table in Intel 8086: Hardware, Software, and Exception Handling
A deep dive into 8086 interrupt processing: the 1 KB Interrupt Vector Table (IVT), dedicated Type 0–4 exceptions, hardware NMI/INTR lines, the 6-step interrupt response cycle, and the IRET sequence.
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Part 8: Intel 8086 Pin Configuration, Operating Modes (Min/Max), and Comprehensive Instruction Set
Exhaustive hardware guide to the 40-pin Intel 8086: multiplexed address/data pins, Minimum Mode uniprocessor vs Maximum Mode multiprocessor circuits with the 8288 bus controller, and complete instruction set categorization.
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