Part 12: Programmable Peripheral Interface ICs: Architecture and Pin Configuration of 8255, 8259, 8254, 8251, and 8257

1. Intel 8255 Programmable Peripheral Interface (PPI)

The 8255 is a general-purpose programmable I/O device configured into 24 I/O pins organized as three 8-bit ports (Port A, Port B, Port C) grouped into Group A and Group B:

2. Intel 8259 Priority Interrupt Controller (PIC)

The 8259 manages up to 8 vectored priority interrupts on a single chip, cascading up to 64 vectored interrupts across a master-slave configuration (1 Master 8259 + 8 Slave 8259s connected via cascade lines CAS0-CAS2):

3. Intel 8254 Programmable Interval Timer (PIT)

The 8254 contains three independent 16-bit counters (Counter 0, 1, 2) that decrement from a preloaded count down to zero at clock input frequencies up to 10 MHz. It provides six programmable operational modes:

• Mode 0: Interrupt on Terminal Count (Output drops LOW upon mode load, goes HIGH when counter reaches zero).
• Mode 1: Hardware Retriggerable One-Shot (Generates clean one-shot pulse on GATE trigger).
• Mode 2: Rate Generator (Frequency divider; outputs a single-clock-wide pulse once every $N$ input clock periods).
• Mode 3: Square Wave Generator (Outputs continuous 50% duty cycle square wave; used for PC system timers and baud rate generators).
• Mode 4: Software Triggered Strobe (Outputs low strobe pulse upon counter completion).
• Mode 5: Hardware Triggered Strobe (Outputs low strobe triggered by rising edge on GATE).

4. Intel 8257 / 8237 Direct Memory Access (DMA) Controller

When bulk data must be transferred at high speeds between memory and high-throughput peripherals (hard drives, network interfaces, graphic framebuffers), routing every byte through CPU registers creates an unacceptable bus bottleneck.

The DMA Controller solves this by taking direct mastership of the system buses:

1. The peripheral asserts a DMA Request (DREQ) to the 8257.
2. The 8257 asserts the CPU's HOLD pin.
3. The CPU completes its current bus cycle, floats its address, data, and control pins into high-impedance state, and asserts HLDA (Hold Acknowledge).
4. The 8257 takes control of the system bus, asserts DACK (DMA Acknowledge) to the peripheral, outputs the physical memory address, and asserts simultaneous MEMR# and IOW# (or IOR# and MEMW#), transferring data directly between memory and peripheral in a single bus cycle without passing through CPU registers.