Engineering Articles

The Draftsbook Blog

Articles, deep dives, and notes from the engineering community.

Mar 6, 20268 min read

Part 2: Asynchronous JavaScript in Depth: The Event Loop, Promises & Async/Await

Master asynchronous JavaScript architecture, the browser and libuv Event Loop, microtasks vs macrotasks, Promise combinators, and AbortController.

By Md. Harun-Or-Roshid

Mar 5, 20269 min read

Part 1: The JavaScript Engine & Execution Context: Scopes, Closures & Memory Management

Master the V8 JavaScript engine pipeline, execution contexts, hoisting in the TDZ, lexical closures, memory heaps, and garbage collection algorithms.

By Md. Harun-Or-Roshid

Mar 4, 20268 min read

Part 2: CSS Custom Properties, Fluid Typography & Modern Performance Animations

Master CSS custom properties, clamp fluid typography formulas, design token architectures, and 60fps GPU compositor animation performance.

By Md. Harun-Or-Roshid

Mar 3, 20268 min read

Part 1: Flexbox vs. CSS Grid: Solving Real-World Responsive Layout Architecture

Master 1D Flexbox vs 2D CSS Grid layout architecture, zero-media-query grids, Subgrid alignment, and modern container queries for responsive engineering.

By Md. Harun-Or-Roshid

Mar 2, 20268 min read

Part 2: Modern HTML5 Forms: Deep Dive into Form Validation, Custom Controls & Security

Master modern HTML5 forms, native Constraint Validation API, accessible custom controls, mobile virtual keyboards, and enterprise data security standards.

By Md. Harun-Or-Roshid

Mar 1, 20264 min read

Part 12: Programmable Peripheral Interface ICs: Architecture and Pin Configuration of 8255, 8259, 8254, 8251, and 8257

The ultimate hardware reference for microprocessor peripheral interface adapters: complete architecture, pin configurations, and control word programming for the 8255 PPI, 8259 PIC, 8254 PIT, 8251 USART, and 8257 DMA controller.

By Md. Harun-Or-Roshid

Mar 1, 20265 min read

Part 11: Intel 8051 Microcontroller Architecture: Harvard Memory Map, SFRs, and I/O Port Circuits

A master-level architectural analysis of the Intel 8051 microcontroller: Microprocessor vs Microcontroller paradigm, Harvard memory organization, 128-byte internal RAM layout, SFR registers, and internal circuits of Ports 0–3.

By Md. Harun-Or-Roshid

Mar 1, 20264 min read

Part 10: Multiprocessor Configurations, 8087 Numeric Coprocessor, and Memory/IO Interfacing

Architectural principles of multiprocessor systems: closely vs loosely coupled topologies, hardware bus arbitration, the Intel 8087 floating-point NDP, and memory-mapped vs isolated I/O interfacing.

By Md. Harun-Or-Roshid

Mar 1, 20264 min read

Part 9: Interrupt Structures and Vector Pointer Table in Intel 8086: Hardware, Software, and Exception Handling

A deep dive into 8086 interrupt processing: the 1 KB Interrupt Vector Table (IVT), dedicated Type 0–4 exceptions, hardware NMI/INTR lines, the 6-step interrupt response cycle, and the IRET sequence.

By Md. Harun-Or-Roshid

Mar 1, 20264 min read

Part 8: Intel 8086 Pin Configuration, Operating Modes (Min/Max), and Comprehensive Instruction Set

Exhaustive hardware guide to the 40-pin Intel 8086: multiplexed address/data pins, Minimum Mode uniprocessor vs Maximum Mode multiprocessor circuits with the 8288 bus controller, and complete instruction set categorization.

By Md. Harun-Or-Roshid

Mar 1, 20265 min read

Part 7: Intel 8086 16-Bit Microprocessor Architecture: BIU, EU, Segmented Memory, and Instruction Pipelining

A comprehensive architectural deep-dive into the Intel 8086: Bus Interface Unit (BIU), Execution Unit (EU), 6-byte instruction prefetch queue, 1 MB segmented physical memory calculations, and comparison with 8085.

By Md. Harun-Or-Roshid

Mar 1, 20263 min read

Part 6: Industrial and Everyday Applications of Microprocessors: From Automotive ECUs to IoT Smart Systems

Explore how microprocessors power real-world engineering systems: automotive Engine Control Units (ECUs), industrial robotics, medical telemetry, smart grid meters, and consumer IoT edge nodes.

By Md. Harun-Or-Roshid