Part 7: Intel 8086 16-Bit Microprocessor Architecture: BIU, EU, Segmented Memory, and Instruction Pipelining

1. Two Independent Functional Units: BIU and EU

In earlier processors like the 8085, the CPU executed instructions strictly serially: it fetched an instruction from memory, waited while internal logic decoded and executed it, and only then fetched the next opcode. During execution, the external memory bus remained idle.

The 8086 fundamentally solved this bus latency bottleneck by dividing its silicon architecture into two asynchronous, independently functioning units: the Bus Interface Unit (BIU) and the Execution Unit (EU).

2. Instruction Pipelining in the 8086

The 6-byte FIFO queue in the BIU forms an elementary two-stage instruction pipeline:

• Whenever at least 2 bytes in the queue become empty and the EU does not require the system bus for operand memory access, the BIU automatically executes an instruction prefetch cycle.
• When the EU completes an instruction, it instantly fetches the next opcode from the front of the queue in zero clock cycles, eliminating the traditional opcode fetch delay.
• Pipeline Stall / Branch Penalty: If a jump (JMP), conditional branch (JZ, JNZ), call (CALL), or interrupt occurs, the target address lies outside the sequential queue. The entire 6-byte queue must be invalidated (flushed), and the BIU must initiate a full bus cycle to fetch from the new target address.

3. Memory Segmentation & 20-Bit Physical Address Calculation

The 8086 has a 20-bit address bus, enabling access to $2^{20} = 1,048,576\text{ bytes} = 1\text{ MB}$ of memory. However, all internal registers (including IP, SP, SI, DI) are only 16 bits wide ($2^{16} = 64\text{ KB}$).

To bridge this disparity, Intel adopted Memory Segmentation. The 1 MB physical memory space is divided into logical segments of up to 64 KB each. At any moment, the processor can actively address four distinct 64 KB segments:

• Code Segment (CS): Contains program instructions. Paired with Instruction Pointer (CS:IP).
• Data Segment (DS): Houses global and static program variables. Paired with general offsets (DS:SI, DS:BX).
• Stack Segment (SS): Stores return addresses, passed parameters, and local variables. Paired with Stack Pointer (SS:SP) and Base Pointer (SS:BP).
• Extra Segment (ES): Provides auxiliary data storage, particularly for destination strings in string operations (ES:DI).

4. Intel 8085 vs. Intel 8086: Comparative Matrix