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advanced~10h
Fundamentals of Computer Architecture & Organization
A comprehensive 10-part engineering curriculum covering interconnection structures, system buses, ALU carry-lookahead adders, IEEE 754 floating-point, single-cycle and multi-cycle datapaths, 5-stage RISC instruction pipelining, hazards and branch prediction, cache hierarchies and MESI coherence, virtual memory and TLBs, RISC vs CISC and open RISC-V, vector SIMD, and multicore NUMA architectures.
Start readingPosts in this series
- 1Part 1: Interconnection Structures: System Buses, PCIe & Crossbar Switches
- 2Part 2: Arithmetic Logic Unit (ALU) Design & IEEE 754 Floating-Point Arithmetic
- 3Part 3: Processor Datapath Design: Single-Cycle, Multi-Cycle & Control Units
- 4Part 4: Instruction Pipelining: The Classic 5-Stage RISC Processor Datapath
- 5Part 5: Pipeline Hazards: Structural, Data Forwarding & Branch Prediction
- 6Part 6: Memory Hierarchy & Cache Coherence: L1/L2/L3 & The MESI Protocol
- 7Part 7: Virtual Memory: Multi-Level Paging, Page Faults & TLB Translation
- 8Part 8: Instruction Set Architecture: CISC vs RISC & The Open RISC-V Standard
- 9Part 9: SIMD Vector Processors & GPU Massively Parallel Compute Engines
- 10Part 10: Multicore Systems: SMP, NUMA Architecture & Amdahl's Law Scaling