SIMD Vector Processors & GPU Architecture

Data-Level Parallelism & Accelerated Compute

Traditional microprocessors are optimized primarily for latency: minimizing the time required to complete a single serial thread of execution using branch predictors, out-of-order execution engines, and deep cache hierarchies. However, modern workloads—artificial intelligence neural networks, computer graphics rendering, video encoding, and cryptographic hashing—exhibit massive Data-Level Parallelism (DLP) where the exact same mathematical operation is applied concurrently across millions of data elements. In this article, we examine Flynn's Taxonomy, analyze CPU vector extensions (AVX-512 and RISC-V Vector), and dissect GPU SIMT (Single Instruction, Multiple Threads) architecture.

1. Flynn's Taxonomy of Computer Architectures

In 1966, Michael J. Flynn classified computer architectures along two independent dimensions: the number of concurrent Instruction Streams and Data Streams:

SISD (Single Instruction, Single Data)

Traditional sequential scalar uniprocessor executing one instruction at a time on one data operand.

SIMD (Single Instruction, Multiple Data)

A single control instruction broadcasts to multiple processing execution lanes operating in lockstep across vector arrays.

MISD (Multiple Instruction, Single Data)

Multiple instructions operating on the same data stream. Rare; utilized in fault-tolerant space flight computers.

MIMD (Multiple Instruction, Multiple Data)

Modern multi-core processors and distributed server clusters running independent programs on different data.

2. CPU Vector Extensions: AVX-512 & Vector Lane Striping

Modern CPU architectures incorporate wide vector registers (128-bit NEON, 256-bit AVX2, 512-bit AVX-512) directly alongside their scalar ALUs. A single 512-bit vector register can be partitioned into:

$16 \times 32\text{-bit single-precision floats}$
$8 \times 64\text{-bit double-precision floats}$
$64 \times 8\text{-bit integers}$ (crucial for INT8 deep learning inference)

A single vector instruction (e.g. _mm512_add_ps) commands 16 physical floating-point ALU lanes simultaneously, computing 16 additions in a single clock cycle and yielding a theoretical 16x compute speedup over scalar execution.

3. GPU Architecture: The SIMT Execution Model

While a modern server CPU dedicates the majority of its silicon die area to huge L3 caches and complex out-of-order execution logic to minimize thread latency, a Graphics Processing Unit (GPU) devotes over 80% of its silicon transistors directly to thousands of arithmetic ALUs, optimizing purely for throughput.

GPUs execute code using the SIMT (Single Instruction, Multiple Threads) paradigm, pioneered by NVIDIA in CUDA:

Streaming Multiprocessors (SM): The core execution cluster of a GPU, containing dozens of CUDA cores, Tensor cores, and high-speed shared scratchpad memory.
Warps / Wavefronts: Threads are grouped into hardware bundles of 32 threads (NVIDIA Warp) or 64 threads (AMD Wavefront) that execute the exact same instruction synchronously.
Zero-Overhead Latency Hiding: When Warp 0 encounters a high-latency DRAM memory read (which can take 400 clock cycles), the hardware warp scheduler instantly switches in zero cycles to Warp 1, Warp 2, or Warp 3, keeping arithmetic units 100% saturated.