Part 3: Processor Datapath Design: Single-Cycle, Multi-Cycle & Control Units

1. State Elements & Combinational Blocks

A datapath is constructed from two distinct classes of digital logic components:

• State (Sequential) Elements: Storage devices whose outputs reflect internal memory latched on active clock edges (D flip-flops). Key state elements include the Program Counter (PC), the Register File (dual-read, single-write multiport memory), and Data Memory (RAM).
• Combinational Elements: Logic blocks that operate purely on current inputs without memory (e.g. ALU, Adders, Multiplexers, and Sign-Extension Units).

2. Single-Cycle Datapath: Strengths & Inefficiencies

In a Single-Cycle Processor, every instruction begins and finishes its complete execution lifecycle (Instruction Fetch → Decode → ALU → Memory Access → Register Write-Back) within exactly one clock cycle:

The Clock Period Dilemma: In synchronous digital systems, the master clock period must be engineered to accommodate the critical path—the longest possible propagation delay required by the slowest instruction in the Instruction Set Architecture (ISA).

Because Load Word (LW) requires 800 ps, the clock period for every instruction must be set to at least 800 ps (capping frequency at 1.25 GHz). Faster instructions (such as branches taking only 500 ps) are forced to waste 300 ps idling.

3. Multi-Cycle Datapath: Resource Sharing & Variable CPI

The Multi-Cycle Datapath breaks down instruction execution into multiple shorter clock cycles (e.g. 200 ps each). An instruction executes across only as many cycles as it strictly requires:

• Branch instructions complete in 3 cycles ($3 \times 200\text{ ps} = 600\text{ ps}$).
• R-type instructions complete in 4 cycles ($4 \times 200\text{ ps} = 800\text{ ps}$).
• Load instructions complete in 5 cycles ($5 \times 200\text{ ps} = 1000\text{ ps}$).

Hardware Reuse: Because different functional units are active in different clock cycles, a multi-cycle datapath can share a single unified memory block for both instructions and data, and reuse a single ALU for both PC incrementing and arithmetic, substantially reducing chip die area.

4. Control Unit Synthesis: Hardwired vs. Microprogrammed