Part 4: Instruction Pipelining: The Classic 5-Stage RISC Processor Datapath

1. The Assembly Line Analogy & Pipelining Throughput

Consider a laundry facility with four sequential steps: Wash (30 min), Dry (40 min), Fold (20 min), and Stash (20 min). Washing a single load of laundry takes $30+40+20+20 = 110\text{ minutes}$.

• Sequential Processing: 4 loads take $4 \times 110\text{ min} = 440\text{ minutes}$ (over 7 hours).
• Pipelined Processing: As soon as Load 1 moves to the dryer, Load 2 enters the washer. Once the pipeline fills, a fresh clean load exits every 40 minutes (the duration of the slowest stage).

Key Architectural Invariant: Pipelining does not reduce the individual latency required to execute a single instruction; rather, it exponentially increases total instruction throughput (instructions retired per second).

2. The Classic 5-Stage RISC Architecture

3. Inter-Stage Pipeline Registers (Latches)

In an unpipelined datapath, signals flow continuously through combinational logic. In a pipelined processor, because five instructions are active simultaneously, data and control signals from stage $k$ must be isolated from stage $k+1$ across clock transitions.

This isolation is achieved by inserting four synchronous Pipeline Registers between the stages:

• IF/ID Register: Latches the fetched 32-bit instruction and incremented PC.
• ID/EX Register: Latches register operands $Rs1, Rs2$, immediate offset, control signals, and destination register address $Rd$.
• EX/MEM Register: Latches the ALU result, store data, zero flag, and branch target address.
• MEM/WB Register: Latches loaded memory data, ALU result, and write-back control flags.

4. Pipelining Performance & Mathematical Speedup

Let $k$ be the number of pipeline stages ($k=5$), and $n$ be the number of instructions executed.

As $n \to \infty$, the theoretical speedup ratio approaches the number of pipeline stages $k$:

In an ideal pipeline without pipeline stalls, the Cycles Per Instruction (CPI) equals exactly $1.0$. However, real-world instruction streams encounter dependencies and conflicts termed pipeline hazards, which we analyze in Part 5.