8085 microprocessor Instruction and Data Formats.
There are numerous techniques to require data for instructions are:
- In the instruction itself 8-bit or 16-bit data may be directly given.
- In the instruction itself, the address of the memory location, I/O port or I/O device, where data resides, may be given.
- In some instructions, only one register is specified. The content of the specified register is one of the operands.
- Some instructions specify two registers and contents of the registers are the required data.
- In some instructions, data is implied and in the most instructions of this type operate on the content of the accumulator.
To specify various kind of data for instructions, the machine codes of all instructions are not of the same length. It may vary as 1-byte, 2-byte or 3-byte instruction.
8085 microprocessor Addressing Modes
Each instruction requires some data on that it has to operate. There are different techniques which are called addressing modes. Intel 8085 uses the following addressing modes:
- Direct Addressing
In this addressing mode, the address of the operand or data is given in the instruction itself.
Example
STA 2400H: This stores the content of the accumulator in the memory location 2400H.
32, 00, 24: The above instruction in the code form.
In the above instruction, 2400H is the memory address for data stored given in the instruction itself. The 2nd and 3rd bytes of the instruction specify the address of the memory location. It is clear, that the source of the data is accumulator.
- Register Addressing
In register addressing mode, the operand is in one of the general-purpose registers. The opcode specifies the address of the register(s) in addition to the operation to be performed.
Example:
MOV A, B: Move the content of B register to register A.
78: The instruction in the code form.
In the above MOV A, B is 78H. In addition the operation to be performed the opcode also specifies source and destination registers.
The opcode 78H can be printed in binary form as 01111000. The first two bits, i.e. 0 1 are for MOV operation, the next three bits 1 1 1 are the binary code for register A, and the last three bits 000 are the binary code for register B.
- Register Indirect Addressing
The Register Indirect mode of addressing operand is specified by a register pair.
Example
- LXI H, 2500 H – Load H-L pair with 2500H.
- MOV A, M – Move the content of the memory location, whose address is in H-L pair (i.e. 2500 H) to the accumulator.
- HLT – Halt.
In the above program MOV A, M is register indirect addressing. This instruction, the operand is in the memory. The address of the memory is not directly given in the instruction. The address of the memory resides in H-L pair and this has already been specified by an earlier instruction in the program, i.e. LXI H, 2500 H.
- Immediate Addressing
In this addressing mode the operand is specified within the instruction itself.
Example
immediate addressing. 2500 is 16-bit data which is given in the instruction itself. It is to be loaded into H-L pair.
- Implicit Addressing
There are certain instructions which operate on the content of the accumulator. Such instructions do not require the address of the operand.
Example
CMA, RAL, RAR, etc.
Status Flags
There is a set of five flip-flops which indicate status (condition) arising after the execution of arithmetic and logic instructions. These are:
- Carry Flag (CS)
- Parity Flag (P)
- Auxiliary Carry Flags (AC)
- Zero Flags (Z)
- Sign Flags (S)
Symbols and Abbreviations:
The symbol and abbreviations which have been used while explaining Intel 8085 instructions are as follows:
| Symbol with details | ||
| Addr | 16-bit address of the memory location. | |
| Data | 8-bit data | |
| data 16 | 16-bit data | |
| r, r1, r2 | One of the registers A, B, C, D, E, H or L | |
| A, B, C, D, H, L | 8-bit register | |
| A | Accumulator | |
| H-L | Register pair H-L | |
| B-C | Register pair B-C | |
| D-E | Register pair D-E | |
| PSW | Program Status Word | |
| M | Memory whose address is in H-L pair | |
| H | Appearing at the end of the group of digits specifies hexadecimal, e.g. 2500H | |
| Rp | One of the register pairs. | |
| Rh | The high order register of a register pair | |
| Rl | The low order register of a register pair | |
| PC | 16-bit program counter, PCH is high order 8 bits and PCL low order 8 bits of register PC. | |
| CS | Carry Status | |
| [] | The contents of the register identified within bracket | |
| [ [] ] | The content of the memory location whose address is in the register pair identified within brackets | |
| ^ | AND operation | |
| ∨ | OR operation | |
| ⊕ or ∀ | Exclusive OR | |
| ← | Move data in the direction of arrow | |
| ⇔ | Exchange contents | |
Intel 8085 Instructions:
An instruction of a computer is a command given to the computer to perform a specified operation on given data. In microprocessor, the instruction set is the collection of the instructions that the microprocessor is designed to execute.
The programmer writes a program in assembly language using these instructions. These instructions have been classified into the following groups:
Data Transfer Group:
Instructions which are used to transfer the data from a register to another register from memory to register or register to memory come under this group
| Instruction
Example |
Description | States | Flags | Addressing | Machine Cycles |
| MOV A, B | Move the content of the one register to another | 4 | none | Register | 1 |
| MOV B, M | Move the content of memory to register | 7 | none | Register Indirect | 2 |
| MOV M, C | Move the content of register to memory | 7 | none | Register Indirect | 2 |
| MVI r, data [r] ←dataExample:MVI M, 08 |
Move immediate data to register | 7 | None | Immediate Register | 3 |
| LXI H, 2500H | Load Register pair immediate | 10 | None | Immediate | 3 |
| LDA 2400 H | Load Accumulator direct | 13 | None | Direct | 4 |
| STA 2000H | Store accumulator direct | 13 | None | Direct | 4 |
| LHLD 2500H | Load H-L pair direct | 16 | None | Direct | 5 |
| SHLD 2500 H | Store H-L pair direct | 16 | None | Direct | 5 |
| LDAX B | Load accumulator indirect | 7 | None | Register Indirect | 2 |
| STAX D | Store accumulator indirect | 7 | None | Register Indirect | 2 |
| XCHG [H-L] ↔[D-E] |
Change the contents of H-L with D-E pair | 4 | None | Register | 1 |
Arithmetic Group:
The instructions of this group perform arithmetic operations such as addition, subtraction, increment or decrement of the content of a register or a memory.
| Instruction Example | Explanation | States | Flags | Addre-ssing | Machine Cycles |
| ADD r [A] ←[A]+[r]Example: ADD K |
Add register to accumulator | 4 | All | Register | 1 |
| ADD M [A] ← [A] + [[H-L]]Example: ADD K |
Add memory to accumulator | 7 | All | Register indirect | 2 |
| ACC r [A] ← [A] + [r] + [CS]Ex:ACC K |
Add register with carry to accumulator | 4 | All | Register | 1 |
| ADC K | Add memory with carry to accumulator | 7 | All | Register indirect | 2 |
| ADI 55K | Add immediate data to accumulator | 7 | All | Immediate | 2 |
| ACI 55K | Add with carry immediate data to accumulator | 7 | All | Immediate | 2 |
| DAD K | Add register paid to H-L pair | 10 | CS | Register | 3 |
| SUB K | Subtract register from accumulator | 4 | All | Register | 1 |
| SUB M [A] ← [A] – [[H-L]]Example: SUB K |
Subtract memory from accumulator | 7 | ALL | Register indirect | 2 |
| SBB K | Subtract memory from accumulator with borrow | 7 | All | Register indirect | 2 |
| SUI 55K | Subtract immediate data from accumulator | 7 | All | Immediate | 2 |
| XCHG | Subtract immediate data from accumulator with borrow | 7 | All | Immediate | 2 |
| INR K | Increment register content | 4 | All except carry flag | Register | 1 |
| INR K | Increment memory content | 10 | All except carry flag | Register indirect | 3 |
| DCR K | Decrement register content | 4 | All except carry flag | Register | 1 |
| DCR K | Decrement memory content | 10 | All except carry flag | Register indirect | 3 |
| INX K | Increment memory content | 6 | None | Register | 1 |
| DCX K | Decrement register pair | 6 | None | Register | 1 |
| DAA | Decimal adjust accumulator | 4 | 1 |
Logical Group
The instructions in this group perform logical operation such as AND, OR, compare, rotate, etc.
| Instruction Set | Explanation | States | Flags | Addressing | Machine Cycles |
| ANA r [A] ←[A]∧[r] |
AND register with accumulator | 4 | All | Register | 1 |
| ANA M [A] ←[A]∧[[H-]] |
AND memory with accumulator | 4 | All | Register indirect | 2 |
| ANI data [A] ← [A] ∧ [data] |
AND immediate data with accumulator | 7 | All | Immediate | 2 |
| ORA r [A] ←[A]∨[r] |
OR-register with accumulator | 4 | All | Register | 1 |
| ORA M [A] ←[A]∨[[H-L]] |
OR-memory with accumulator | 7 | All | Register indirect | 2 |
| ORI data [A] ← [A] ∨ [data] |
OR -immediate data with accumulator | 7 | All | Immediate | 2 |
| CMP r [A]-[r] |
Compare register with accumulator | 4 | All | Register | 1 |
| CMP M [A] – [[H-L]] |
Compare memory with accumulator | 7 | All | Register indirect | 2 |
| CPI data [A] – data |
Compare immediate data with accumulator | 7 | All | Immediate | 2 |
| RLC [An+1] ←[An], [A0] ←[A7], [CS] ←[A7] |
Rotate accumulator left | 4 | Cs | Implicit | 1 |
| RRC [A7] ←[A0], [CS] ←[A0], [An] ←[An+1] |
Rotate accumulator right | CS | Implicit | 1 | |
| RAL [An+1] ←[An], [CS] ←[A7], [A0] ←[CS] |
Rotate accumulator left through carry | CS | Implicit | 1 | |
| RAR [An] ←[An+1], [CS] ←[A0], [A7] ←[CS] |
Rotate accumulator right through carry | CS | Implicit | 1 |
Branch Control Group: This group contains the instructions for conditional and unconditional jump, subroutine call and return, and restart.
Others are Unconditional Jump, Conditional Jump, Unconditional CALL, Conditional CALL, Unconditional Return, Conditional Return, Restart, Stack, I/O and Machine Control Group.