8086 Microprocessor

Part 12: Microprocessor Peripheral Devices with PIN Configuration

by Jesmin Akther | Jul 5, 2021 | Microprocessor & Microcontroller

Peripheral Devices

In order to communicate with the outside world microcomputers, use peripherals (I/O devices). Commonly used peripherals are: A/D converter, D/A converter, CRT, printers, Hard disks, floppy disks, magnetic tapes etc. Peripherals are connected to the microcomputer through electronic circuits known as interfacing circuits.

Programmable Peripheral interface (PPI)

A programmable peripheral interface is a multiport device. The ports may be programmed in a variety of ways as required by the programmer. The device is very useful for interfacing peripheral devices. The term PIA, Peripheral Interface Adapter is also used by some manufacturer.

Intel 8255

The Intel 8255 is a programmable peripheral interface (PPI). It has two versions, i.e. the Intel 8255A and Intel 8255A-5. General descriptions for both are same. There are some differences in their electrical characteristics. Hereafter, they will be referred to as 8255. Its main functions are to interface peripheral devices to the microcomputer.

It has three 8-bit ports, namely Port A, Port B and Port C. The port C has been further divided into two 4-bit ports, port C upper and Port C lower. Thus a total of 4-ports are available, two 8-bit ports and two 4-bit ports. Each port can be programmed either as an input port or an output port.

Operating Modes of 8255

The Intel 8255 has the following three modes of operation which are selected by software:

Mode 0 – Simple Input/output: The 8255 has two 8-bit ports (Port A and Port B) and two 4-bit ports (Port C_upper and Port C_lower). In Mode 0 operation, a port can be operated as a simple input or output port. Each of the 4 ports of 8255 can be programmed to be either an input or output port.

Mode 1-Strobed Input/output: Mode 1 is strobed input/output mode of operation. The Port A and Port B both are designed to operate in this mode of operation. When Port A and Port B are programmed in Mode 1, six pins of Port C are used for their control.

Mode 2 -Bidirectional Port: Mode 2 is strobed bidirectional mode of operation. In this mode Port A can be programmed to operate as a bidirectional port. The mode 2 operation is only for Port A. When Port A is programmed in Mode 2, the port B can be used either Mode 1 or Mode 0.

Architecture of Intel 8255

Intel 8255A pin description

It is a 40 pin I.C. package. It operates on a single 5 V_d.c. supply. Its important characteristics are as follows:

Ambient temperature 0 to 70₀C, Voltage on any pin: 0.5 V to 7 V. Power dissipation 1 Watt V_IL = Input low voltage = Minimum 0.5 V, Maximum 0.8 V. V_IH = Input high voltage = Minimum 2 V, Maximum Vcc. V_OL = Output low voltage = 0.45 V V_OH = Output High Voltage = 2.4 V I_DR = Darlington drive connect = Minimum 1 mA, Maximum 4 mA of any 8 pins of the port.

The pins of various ports are as follows:

PA₀ – PA₇ 8 Pins of port A PB₀ – PB₇ 8 pins of port B PC₀ – PC₃ 4 pins of port C_lower PC₄ – PC₇ 4 pins of Port C_upper

The important control signals are:

CS (Chip Select): It is a chip select signal. The LOW status of this signal enables communication between the CPU and 8255.

RD (READ): When RD goes LOW the 8255 sends out data or status information to the CPU on the data bus. In other words it allows the CPU to read data from the input port of 8255.

WR (Write): When WR goes LOW the CPU writes data or control word into 8255. The CPU writes data into the output port of 8255 and the control word into the control word register.

RESET: RESET is an active high signal. It clears the control register and sets all ports in the input mode.

A0 and A1: The selection of input port and control word register is done using A0 and A1 in conjunction with RD and WR. A0 and A1 are normally connected to the least significant bits of the address bus. If two 8255 units are used the addresses of ports are as follows:

For the First unit of 8255, i.e. 8255.1:

Port/Control word register	Port/Control word register Address
Port A	00
Port B	01
Port C	02
Control word register	03

For the 2nd unit of 8255, i.e. 8255.2:

Port/Control word register	Port/Control word register Address
Port A	08
Port B	09
Port C	0A
Control word register	0B

8253 Programmable Interval Timer

A programmable counter or interval timer is used in real time application for timing and counting function such as BCD or binary counting, generation of accurate time delay, generation of square wave of desired frequency, rate generation, hardware/software triggered strobe signal, one shot signal of wanted width etc.

Popular programmable interval timer chips are Intel 8253 and 8254. Both are pin to pin compatible and operate in the following six modes:

Mode 0: Interrupt on terminal count

Mode 1: Programmable one-shot

Mode 2: Rate generator

Mode 3: Square wave generator

Mode 4: Software triggered mode

Mode 5: Hardware triggered mode

The 8254 is compatible to 8086, 8088, 8085 and most other microprocessors. The 8253 is compatible to 8085 microprocessor. The 8254 is superset of the 8253.

Architecture of Intel 8253/54

Intel 8253

The 8253 is 24-pin IC and operates at 5 Vd.c.. It contains three independent 16-bit counters. The programmer can program 8253 to operate in any one of the 6 operating modes. It operates under software control.

The description of its important pins is as follows:

RD (Read): When this pin is LOW the CPU reads data.

WR: (Write): When this is low, the CPU outputs data in the form of mode information or loading of counters.

A₀, A1: These pins are connected to the address bus. These are used to select one of three counters. These are also used to address the control word registers for mode selection.

CS: Chip Select.

D₀ – D₇: Bidirectional data bus.

CLK₀, CLK₁ and CLK₂ are clock for Counter 0, Counter 1 and Counter 2 respectively.

GATE₀, GATE₁ and GATE₂ are gate terminals of Counter 0, Counter 1 and Counter 2 respectively.

OUT₀, OUT₁ and OUT₂ are output terminals of Counter 0, Counter 1 and Counter 2 respectively.

The 8253 contains a data buffer, read/write logic and control word register as described below:

Data Bus Buffer: This buffer is within 8253. It is a 3-state, bidirectional, 8-bit buffer. It is used to interface 8253 to the system data bus through D₀ – D₇ lines.

Read/Write logic: The 8253 contains a read/write logic which accepts input from the system bus and then makes control signals for the operation of 8253. The following table displays the status of pins associated with read/write logic for several controls:

CS	A1	A0	RD	WR	Result
0	0	0	0	1	Read Counter No. 0
0	0	1	0	1	Read Counter No. 1
0	1	0	0	1	Read Counter No. 2
0	0	0	1	0	Read Counter No. 0
0	0	1	1	0	Read Counter No. 1
0	1	0	1	0	Read Counter No. 2
0	1	1	1	0	Write Mode word
0	1	1	0	1	No-operation 3 state
0	X	X	1	1	No-operation 3 state
0	X	X	X	X	Disable 3 -state

Keep it mind, X indicates undefined state. It means that it does not matter whether the state is 0 or 1.

Counter Word Register: When the pins A0, A1 are 11, the control word register is selected. The control word format is shown below:

D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀

SC1

SC0

RL1

RL0

BCD

The bits D₇ and D₆ of the control word are to select one of the 3 counters. D₅ and D₄ are for loading/reading the count. D₃, D₂ and D₁ are for the selection of operating mode of the selected counter. These are six modes of operation for each counter of 8253. The six modes of operation are: MODE 0, MODE 1, MODE 2, MODE 3, MODE 4 and MODE 5. The bit D0 is for the selection of binary or BCD counting.

8253/54 Operational Modes

8253/54 can be operated in 6 different modes. These modes are:

MODE 0 : Interrupt on Terminal Count

Mode 0 is used for the generation of accurate time delay under software control.
One of the counters of 8253 is initialized and loaded with suitable count for the desired time delay.
When counting is finished the counter interrupts the CPU. On interruption the microprocessor completes the required task which is to be performed after the desired time delay.
For MODE 0 operation GATE is kept high. While counting is going on the counter output OUT remains LOW. When the terminal count is reached i.e. count reaches 0, the output becomes HIGH until the count is reloaded or new count is loaded.
When the count is reloaded or OUT becomes LOW and the counter starts its counting operation again.

MODE 1 : Programmable One-Shot

In MODE 1 the counter acts as a retriggerable and programmable one-shot.
The LOW to HIGH transition of the signal applied to GATE acts as a trigger signal.
In this mode of operation OUT becomes firstly HIGH after the mode is set. After mode set operation the counter is loaded by a count value of N. The counter decrements count, and the output (OUT) goes LOW for N clock cycles for every LOW to HIGH transition of the GATE input.

MODE 2 : RATE Generator

In MODE 2 the counter acts as a simple divide by N counter.
When this mode is set the output of the counter turn out to be firstly HIGH.
After mode set operation the counter is loaded by a count of value N.
For MODE 2 operation GATE is kept HIGH.
In this mode the output remains HIGH for (N-1) clock pulses and then goes LOW for one clock pulse.

MODE 3 : Square Wave Generation

In MODE 3 the counter acts as a square wave generator. After mode set operation the counter is loaded by a count of value N.
For MODE 3 operation GATE is kept back HIGH.
For even values of N the output remains HIGH for N/2 clock pulses abd then goes LOW for next N/2 clock pulses.

MODE 4 : Software Triggered Strobe

In MODE 4 operation the output of the counter becomes firstly HIGH after the mode is set.
GATE is kept HIGH for this mode of operation. The counter begins counting instantly after the count is loaded into the count register.
When the counter reaches terminal count (i.e. counter content = 0) the output goes LOW for one clock period, then it returns to HIGH.
The output signal may be used as strobe.
This mode of operation is referred to as a software triggered strobe because the generation of the strobe signal is triggered by loading the count into the count register.

MODE 5 : Hardware Triggered Strobe

operation GATE input acts as a trigger.
After the mode is set, the output becomes initially HIGH.
A count value of N is loaded into the counter.
a LOW to HIGH transition of the GATE input the counter starts decrementing the count.
The counting begins at the first negative edge of the clock after the rising edge of the GATE input.
On terminal count the output goes LOW for one clock period, and then it goes HIGH again.
the LOW to HIGH transition of the GATE input causes triggering, this mode is referred to as hardware triggered strobe.

Part 8: 8086 Microprocessor PIN Configuration and Instruction Set

by Jesmin Akther | Jul 4, 2021 | Microprocessor & Microcontroller

8086 pins configuration

The description of the pins of 8086 is as follows:

Address Data Bus PIN in details:

AD0-AD15 (Address Data Bus): Bidirectional address/data lines. These are low order address bus. They are multiplexed with data. When these lines are used to transmit memory address, the symbol A is used instead of AD, for example, A0- A15.

A16 – A19 (Output): High order address lines. These are multiplexed with status signals.

A16/S3, A17/S4: A16 and A17 are multiplexed with segment identifier signals S3 and S4.

A18/S5: A18 is multiplexed with interrupt status S5.

A19/S6: A19 is multiplexed with status signal S6.

BHE/S7 (Output):

Bus High Enable/Status. During T1, it is low. It enables the data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE signal. It is multiplexed with status signal S7. S7 signal is available during T3 and T4.

RD (Read):

For read operation. It is an output signal. It is active when LOW. Ready (Input): The addressed memory or I/O sends acknowledgment through this pin. When HIGH, it denotes that the peripheral is ready to transfer data.

RESET (Input): System reset. The signal is active HIGH.

CLK (input): Clock 5, 8 or 10 MHz

INTR: Interrupt Request.

NMI (Input): Non-maskable interrupt request.

TEST (Input): Wait for test control. When goes to LOW the microprocessor continues execution otherwise waits.

VCC: Power supply +5V dc.

GND: Ground.

Operating Modes of 8086

There are two operating modes of operation for Intel 8086, namely the minimum mode and the maximum mode. When only one 8086 CPU is to be used in a microprocessor system, the 8086 is used in the Minimum mode of operation. In a multiprocessor system 8086 operates in the Maximum mode.

Pin Description for Minimum Mode

In this minimum mode of operation, the pin MN/MX is connected to 5V D.C. supply i.e. MN/MX = VCC.

The description about the pins from 24 to 31 for the minimum mode is as follows:

INTA (Output):

Pin number 24 interrupts acknowledgement. On receiving interrupt signal, the processor issues an interrupt acknowledgment signal. It is active LOW.

ALE (Output):

Pin no. 25. Address latch enable. It goes HIGH during T1. The microprocessor 8086 sends this signal to latch the address into the Intel 8282/8283 latch.

DEN (Output):

Pin no. 26. Data Enable. When Intel 8287/8286 octal bus transceiver is used this signal. It is active LOW.

DT/R (output):

Pin No. 27 data Transmit/Receives. When Intel 8287/8286 octal bus transceiver is used this signal controls the direction of data flow through the transceiver. When it is HIGH, data is sent out. When it is LOW, data is received.

M/IO (Output):

Pin no. 28, Memory or I/O access. When this signal is HIGH, the CPU wants to access memory. When this signal is LOW, the CPU wants to access I/O device.

WR (Output): Pin no. 29, Write. When this signal is LOW, the CPU performs memory or I/O write operation.

HLDA (Output):

Pin no. 30, Hold Acknowledgment. It is sent by the processor when it receives HOLD signal. It is active HIGH signal. When HOLD is removed HLDA goes LOW.

HOLD (Input):

Pin no. 31, Hold. When another device in microcomputer system wants to use the address and data bus, it sends HOLD request to CPU through this pin. It is an active HIGH signal.

Pin Description for Maximum Mode

In the maximum mode of operation, the pin MN/¯MX is made LOW. It is grounded. The description about the pins from 24 to 31 is as follows:

QS1, QS0 (Output): Pin numbers 24, 25, Instruction Queue Status. Logics are given below:

QS1	QS0	Operation
0	0	No operation
0	1	1^st byte of opcode from queue.
1	0	Empty the queue
1	1	Subsequent byte from queue

S0, S1, S2 (Output):

Pin numbers 26, 27, 28 Status Signals. These signals are connected to the bus controller of Intel 8288. This bus controller generates memory and I/O access control signals. Logics for status signal are given below:

S2	S1	S0	Operation
0	0	0	Interrupt acknowledgement
0	0	1	Read data from I/O port
0	1	0	Write data from I/O port
0	1	1	Halt
1	0	0	Opcode fetch
1	0	1	Memory read
1	1	0	Memory write
1	1	1	Passive state

LOCK (Output):

Pin no. 29. It is an active LOW signal. When this signal is LOW, all interrupts are masked and no HOLD request is granted. In a multiprocessor system all other processors are informed through this signal that they should not ask the CPU for relinquishing the bus control.

RG/GT1, RQ/GT0 (Bidirectional):

Pin numbers 30, 31, Local Bus Priority Control. Other processors ask the CPU by these lines to release the local bus. In the maximum mode of operation signals WR, ALE, DEN, DT/R etc. are not available directly from the processor. These signals are available from the controller 8288.

The 8086 microprocessor supports 8 types of instructions

Data Transfer Instructions
Arithmetic Instructions
Bit Manipulation Instructions
String Instructions
Program Execution Transfer Instructions (Branch & Loop Instructions)
Processor Control Instructions
Iteration Control Instructions
Interrupt Instructions

Data Transfer Instructions:

These instructions are used to transfer the data from the source operand to the destination operand. Following are the list of instructions under this group:

Instruction to transfer a word

MOV: Used to copy the byte or word from the provided source to the provided destination.

PPUSH: Used to put a word at the top of the stack.

POP: Used to get a word from the top of the stack to the provided location.

PUSHA: Used to put all the registers into the stack.

POPA: Used to get words from the stack to all registers.

XCHG: Used to exchange the data from two locations.

XLAT: Used to translate a byte in AL using a table in the memory.

Instructions for input and output port transfer

IN: Used to read a byte or word from the provided port to the accumulator.

OUT: Used to send out a byte or word from the accumulator to the provided port.

Instructions to transfer the address

LEA: Used to load the address of operand into the provided register.

LDS: Used to load DS register and other provided register from the memory

LES: Used to load ES register and other provided register from the memory.

Instructions to transfer flag registers

LAHF: Used to load AH with the low byte of the flag register.

SAHF: Used to store AH register to low byte of the flag register.

PUSHF : Used to copy the flag register at the top of the stack.

POPF: Used to copy a word at the top of the stack to the flag register.

Arithmetic Instructions

These instructions are used to perform arithmetic operations like addition, subtraction, multiplication, division, etc. Following is the list of instructions under this group:

Instructions to perform addition

ADD: Used to add the provided byte to byte/word to word.
ADC: Used to add with carry.
INC: Used to increment the provided byte/word by 1.
AAA: Used to adjust ASCII after addition.
DAA: Used to adjust the decimal after the addition/subtraction operation.

Instructions to perform subtraction

SUB: Used to subtract the byte from byte/word from word.
SBB: Used to perform subtraction with borrow.
DEC: Used to decrement the provided byte/word by 1.
NPG: Used to negate each bit of the provided byte/word and add 1/2’s complement.
CMP: Used to compare 2 provided byte/word.
AAS: Used to adjust ASCII codes after subtraction.
DAS: Used to adjust decimal after subtraction.

Instruction to perform multiplication

MUL : Used to multiply unsigned byte by byte/word by word.
IMUL: Used to multiply signed byte by byte/word by word.
AAM: Used to adjust ASCII codes after multiplication.

Instructions to perform division
DIV − Used to divide the unsigned word by byte or unsigned double word by word.

IDIV − Used to divide the signed word by byte or signed double word by word.
AAD − Used to adjust ASCII codes after division.
CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower byte.
CWD − Used to fill the upper word of the double word with the sign bit of the lower word.

Bit Manipulation Instructions

These instructions are used to perform operations where data bits are involved, i.e. operations like logical, shift, etc.

Following is the list of instructions under this group:

Instructions to perform logical operation

NOT − Used to invert each bit of a byte or word.
AND − Used for adding each bit in a byte/word with the corresponding bit in another byte/word.
OR − Used to multiply each bit in a byte/word with the corresponding bit in another byte/word.
XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the corresponding bit in another byte/word.
TEST − Used to add operands to update flags, without affecting operands.

Instructions to perform shift operations

SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.
SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into the new MSB.

Instructions to perform rotate operations

ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry Flag [CF].
ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry Flag [CF].
RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to MSB.
RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB.

String Instructions

String is a group of bytes/words and their memory is always allocated in a sequential order.

Following is the list of instructions under this group:

REP − Used to repeat the given instruction till CX ≠ 0.
REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided memory location.
OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided memory location to the I/O port.
SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL or string word with a word in AX.
LODS/LODSB/LODSW − Used to store the string byte into AL or string word into AX.

Program Execution Transfer Instructions (Branch and Loop Instructions)

These instructions are used to transfer/branch the instructions during an execution. It includes the following instructions −

Instructions to transfer the instruction during an execution without any condition:

CALL − Used to call a procedure and save their return address to the stack.
RET − Used to return from the procedure to the main program.
JMP − Used to jump to the provided address to proceed to the next instruction.
Instructions to transfer the instruction during an execution with some conditions −
JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
JAE/JNB − Used to jump if above/not below instruction satisfies.
JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
JC − Used to jump if carry flag CF = 1
JE/JZ − Used to jump if equal/zero flag ZF = 1
JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.
JNC − Used to jump if no carry flag (CF = 0)
JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
JNO − Used to jump if no overflow flag OF = 0
JNP/JPO − Used to jump if not parity/parity odd PF = 0
JNS − Used to jump if not sign SF = 0
JO − Used to jump if overflow flag OF = 1
JP/JPE − Used to jump if parity/parity even PF = 1
JS − Used to jump if sign flag SF = 1

Processor Control Instructions

These instructions are used to control the processor action by setting/resetting the flag values.

Following are the instructions under this group:

STC − Used to set carry flag CF to 1
CLC − Used to clear/reset carry flag CF to 0
CMC − Used to put complement at the state of carry flag CF.
STD − Used to set the direction flag DF to 1
CLD − Used to clear/reset the direction flag DF to 0
STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.

Iteration Control Instructions

These instructions are used to execute the given instructions for number of times. Following is the list of instructions under this group −

LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0
LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0
LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX = 0
JCXZ − Used to jump to the provided address if CX = 0

Interrupt Instructions

These instructions are used to call the interrupt during program execution.

INT − Used to interrupt the program during execution and calling service specified.
INTO − Used to interrupt the program during execution if OF = 1
IRET − Used to return from interrupt service to the main program

Part 7: 8086 Microprocessor Architecture and Functional Unit

by Jesmin Akther | Jul 4, 2021 | Microprocessor & Microcontroller

8086 Microprocessor is a boosted version of 8085 Microprocessor designed by Intel in 1976. This is a 16-bit Microprocessor having 20 address lines and 16 data lines which provides up to 1MB storage. It consists of powerful instruction set provides operations such as multiplication and division easily. It supports two modes of operation such as Maximum mode and Minimum mode. Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for system having a single processor.

Features of 8086

The most prominent features of 8086 microprocessor are as follows:

It has an instruction queue of storing six instruction bytes from the memory resulting in faster processing.
It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data bus resulting in faster processing.
This is available in 3 versions based on the frequency of operation:
1. 8086 → 5MHz
2. 8086-2 → 8MHz
3. (c)8086-1 → 10 MHz
It uses two stages of pipelining, such as Fetch Stage and Execute Stage, which improves performance.
Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
Execute stage executes these instructions.
It has 256 vectored interrupts.
This is consists of 29,000 transistors.

Comparison between 8085 & 8086 Microprocessor

Size: 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.
Address Bus: 8085 has 16-bit address bus while 8086 has 20-bit address bus.
Memory: 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.
Instruction: 8085 doesn’t have an instruction queue, whereas 8086 has an instruction queue.
Pipelining: 8085 doesn’t support a pipelined architecture while 8086 supports a pipelined architecture.
I/O: 8085 can address 2^8 = 256 I/O’s, whereas 8086 can access 2^16 = 65,536 I/O’s.
Cost: The cost of 8085 is low whereas that of 8086 is high.

Architecture of 8086

The following diagram depicts the architecture of 8086 Microprocessor:

8086 Microprocessor is divided into two functional units that is EU (Execution Unit) and BIU (Bus Interface Unit).

Execution Unit

EU gives instructions to BIU stating from where to fetch the data and then decode and execute those instructions. Its function is to control operations on data using the instruction decoder & ALU. EU has no direct connection with system buses as shown in the above figure, it performs operations over data over BIU. Let us now discuss the functional parts of 8086 microprocessors.

ALU

It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.

Flag Register

It is a 16-bit register that behaves like a flip-flop, that is it changes its status according to the result stored in the accumulator. It has 9 flags and they are divided into 2 groups one is Conditional Flags and the other is Control Flags.

Conditional Flags

It represents the result of the last arithmetic or logical instruction executed. Following is the list of conditional flags:

Carry flag:

This flag indicates an overflow condition for arithmetic operations.

Auxiliary flag:

When an operation is performed at ALU, it results in a carry/barrow from lower nibble (that isD0 – D3) to upper nibble (that isD4 – D7), then this flag is set, that is carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to BCD conversion.

Parity flag:

This flag is used to indicate the parity of the result, that is when the lower order 8-bits of the result contains even number of 1’s, then the Parity Flag is set. For odd number of 1’s, the Parity Flag is reset.

Zero flag:

This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0.

Sign flag:

This flag holds the sign of the result, that is when the result of the operation is negative, then the sign flag is set to 1 else set to 0.

Overflow flag:

This flag represents the result when the system capacity is exceeded.

Control Flags

Control flags controls the operations of the execution unit. Following is the list of control flags −

Trap flag:

It is used for single step control and allows the user to execute one instruction at a time for debugging. If it is set, then the program can be run in a single step mode.

Interrupt flag:

It is an interrupt enable/disable flag, that is used to allow/prohibit the interruption of a program. It is set to 1 for interrupt enabled condition and set to 0 for interrupt disabled condition.

Direction flag:

It is used in string operation. As the name suggests when it is set then string bytes are accessed from the higher memory address to the lower memory address and vice-a-versa.

General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers can be used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX, BX, CX, and DX respectively.

AX register:

It is also known as accumulator register. It is used to store operands for arithmetic operations.

BX register:

It is used as a base register. It is used to store the starting base address of the memory area within the data segment.

CX register:

It is referred to as counter. It is used in loop instruction to store the loop counter.

DX register:

This register is used to hold I/O port address for I/O instruction.

Stack pointer register

It is a 16-bit register, which holds the address from the start of the segment to the memory location, where a word was most recently stored on the stack.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses, fetching instructions from the memory, reading data from the ports and the memory as well as writing data to the ports and the memory. EU has no direction connection with System Buses so this is possible with the BIU. EU and BIU are connected with the Internal Bus. It has the following functional parts which are mention below:

Instruction queue:

BIU contains the instruction queue. BIU gets upto 6 bytes of next instructions and stores them in the instruction queue. When EU executes instructions and is ready for its next instruction, then it simply reads the instruction from this instruction queue resulting in increased execution speed. Fetching the next instruction while the current instruction executes is called pipelining.

Segment register:

BIU has 4 segment buses, that is CS, DS, SS& ES. It holds the addresses of instructions and data in memory, which are used by the processor to access memory locations. It also contains 1 pointer register IP, which holds the address of the next instruction to executed by the EU.

CS:

This is stands for Code Segment. It is used for addressing a memory location in the code segment of the memory, where the executable program is stored.

DS:

This is stands for Data Segment. It consists of data used by the program and is accessed in the data segment by an offset address or the content of other register that holds the offset address.

SS:

This is stands for Stack Segment. It handles memory to store data and addresses during execution.

ES:

This is stands for Extra Segment. ES is additional data segment, which is used by the string to hold the extra destination data.

Instruction pointer:

This is is a 16-bit register used to hold the address of the next instruction to be executed.