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Part 7: Bitwise Logic, Masking, and Shift/Rotate Instructions in x86-64

Md. Harun-Or-RoshidNov 5, 20263 min readArticle
Part 7: Bitwise Logic, Masking, and Shift/Rotate Instructions in x86-64

Lesson Overview & Bit Manipulation

Bitwise operations form the foundational bedrock of systems engineering, cryptography, network packet parsing, hardware device driver register control, and graphics algorithms. In assembly language, bitwise manipulation executes directly in the ALU hardware without compiler abstraction overhead. In Part 7, we explore boolean operations (AND, OR, XOR, NOT), non-destructive testing with TEST, logical vs. arithmetic bit shifts (SHL, SHR, SAR), circular rotations (ROL, ROR), and hardware population count instructions.

1. Boolean Logic Instructions

The primary bitwise logic instructions perform bit-by-bit boolean operations on register or memory operands:

MnemonicOperationCommon Systems Programming Idiom
AND dest, srcBitwise AND. Clears bits where src is 0.and rax, 0xFF (mask low byte) and rax, ~15 (align to 16 bytes)
OR dest, srcBitwise OR. Sets bits where src is 1.or rax, (1 << 3) (sets bit 3 active)
XOR dest, srcBitwise Exclusive OR. Inverts bits.xor eax, eax (fast register zeroing!)
NOT destOne's complement inversion (flips all bits).not rbx (inverts all 64 bits, flags unaffected)
TEST dest, srcNon-destructive AND (updates ZF and SF).test rax, rax (checks if pointer is NULL)

Why do modern compilers write xor eax, eax instead of mov rax, 0?

The instruction mov rax, 0 requires a 7-byte encoding (including a 32-bit immediate zero) and introduces a data dependency in the CPU pipeline. In contrast, xor eax, eax requires only 2 bytes of machine code (31 C0). Modern Intel and AMD processors have dedicated hardware "zeroing idioms" in the instruction decoder that clear the register with zero execution latency and without consuming an ALU execution port!

2. Bit Shifts: Logical vs. Arithmetic

Shift instructions displace the bits within a register to the left or right by an immediate count or the value stored in the CL register:

SHL (Shift Left)

Shifts bits left, filling emptied positions with zeroes. Equivalent to multiplying by $2^n$:

shl rax, 3 ; RAX = RAX * 8

SHR (Logical Right)

Shifts bits right for unsigned integers, inserting zeroes into the most significant bits:

shr rax, 2 ; RAX = RAX / 4 (unsigned)

SAR (Arithmetic Right)

Preserves the sign bit (MSB) for signed two's-complement integers during right shift:

sar rax, 1 ; Signed division by 2

3. Advanced Hardware Bit Operations (POPCNT & BSF)

Modern processors include specialized hardware instructions for algorithmic acceleration:

  • POPCNT (Population Count): Counts the number of active 1-bits in a register in 1 cycle: popcnt rax, rbx (critical for chess bitboards and bloom filters).
  • BSF / BSR (Bit Scan Forward / Reverse): Scans for the index of the first or last active bit set: bsf rax, rdi.

Summary & Next Step

Bitwise operations allow fine-grained data manipulation and flag evaluation. In Part 8, we combine arithmetic and bitwise comparisons with conditional jump instructions (JE, JNE, JG, JL) and build high-performance loops with branch prediction awareness.

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Related reading

Bitwise Logic & Shift Instructions in ASM | Draftsbook · Draftsbook